The phase-locked loop (PLL) is a circuit that generates a clock at a controlled frequency. The PLL is used in a wide variety of applications, including frequency synthesis, clock recovery, clock multiplication, and clock regeneration. FIG. 1 illustrates an example block diagram of a PLL 100. The PLL 100 includes a phase-frequency detector (PFD) 110, a charge pump (CP) 120, a filter (e.g., low pass filter (LPF)) 130, and an oscillator 140. The output frequency of the oscillator 140 is controlled by one or more input control signals. In operation, the PLL 100 adjusts the frequency of the oscillator 140 to match (in both frequency and phase) a reference input 160 by periodically charging or discharging the LPF 130 using the CP 120 based on input from the PFD 110. Once matched, the output (controlled clock signal) 165 of the PLL 100 is locked at the frequency of the reference clock 160. The PLL 100 may also include a divider 150 on a feedback loop from the oscillator 140 to the PFD 110. The divider 150 takes the PLL output 165 and divides it by N so that the divided signal 170 is compared to the reference input. This enables the PLL output 165 to be N times higher in frequency than the reference input 160, allowing the PLL 100 to perform frequency multiplication.
Lock time is the time it takes the PLL 100 to generate the controlled clock signal 165 at the desired frequency by locking onto the reference frequency. Decreasing lock time is usually desirable 100. One way to decrease lock time is by increasing the loop bandwidth. However, increasing loop bandwidth may affect the performance of the PLL after lock.